Simplified Floating-Point Division and Square Root
Viitanen, Timo; Jääskeläinen, Pekka; Esko, Otto; Takala, Jarmo (2013)
Institute of Electrical and Electronics Engineers
Julkaisun pysyvä osoite on
Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using ﬁxed-point arithmetic due to expected power and area savings over ﬂoating-point computation. However, recent research shows that ﬂoating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difﬁculties associated with ﬁxed-point arithmetic. This paper investigates the effects of simpliﬁed ﬂoating-point arithmetic applied to an FMA-based ﬂoating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overﬂow-related errors with inexpensive exponent-manipulation special instructions.
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