Efficient Exposed SIMD Datapath Connectivity on FPGAs
Samawat, Malik Quamrus (2020)
Samawat, Malik Quamrus
2020
Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2020-11-18
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202010267472
https://urn.fi/URN:NBN:fi:tuni-202010267472
Tiivistelmä
Field-programmable gate arrays (FPGA) are popular for their ability to be configured and reconfigured at any instant of time. They consist of numerous logic blocks linked with programmable interconnects. FPGAs provide high parallelism, low power consumption, greater efficiency in comparison to most other similar devices available in the market. However, they are very difficult to program for the end-users as programming FPGAs require knowledge regarding hardware design.
Using soft-core processors can somewhat alleviate this issue. Transport-triggered architectures (TTA) can be used for processor designing. FPGAs can be programmed using TTAs as an overlay layer. They have gained popularity due to their exploitation of the parallel programming model. Though they are still under research, yet they have shown promising results in improving execution time, image size, and resource utilization. TTAs are simple to implement in FPGAs and are quite efficient.
TTAs implement instruction-level parallelism through different functional units. Parallel data transports and interconnections are essential to program these function units in parallel. Based on the efficient utilization of this datapath connectivity, the efficiency of TTA architecture in FPGAs can be enhanced quite a bit.
This thesis presents a TTA variation with reduced internal connectivity beyond standard VLIW processors to improve the implementation efficiency measured in terms of clock frequency and resource utilization. It demonstrates an exposed single instruction multiple data (SIMD) datapath connectivity model with a reduced number of connections that can successfully sustain one per cycle operation throughput. Additionally, the performance of this reduced connectivity template is compared with a previously demonstrated architecture based on an equivalent metric. After verification, the findings show promising improvement in terms of clock frequency and resource utilization.
Using soft-core processors can somewhat alleviate this issue. Transport-triggered architectures (TTA) can be used for processor designing. FPGAs can be programmed using TTAs as an overlay layer. They have gained popularity due to their exploitation of the parallel programming model. Though they are still under research, yet they have shown promising results in improving execution time, image size, and resource utilization. TTAs are simple to implement in FPGAs and are quite efficient.
TTAs implement instruction-level parallelism through different functional units. Parallel data transports and interconnections are essential to program these function units in parallel. Based on the efficient utilization of this datapath connectivity, the efficiency of TTA architecture in FPGAs can be enhanced quite a bit.
This thesis presents a TTA variation with reduced internal connectivity beyond standard VLIW processors to improve the implementation efficiency measured in terms of clock frequency and resource utilization. It demonstrates an exposed single instruction multiple data (SIMD) datapath connectivity model with a reduced number of connections that can successfully sustain one per cycle operation throughput. Additionally, the performance of this reduced connectivity template is compared with a previously demonstrated architecture based on an equivalent metric. After verification, the findings show promising improvement in terms of clock frequency and resource utilization.