SIMPLIS efficiency model for a synchronous multiphase buck converter

Abstract

In this master’s thesis, an efficiency model was developed for the synchronous multiphase buck converters of the TPS6594x-Q1 integrated circuit using SIMPLIS simulator. The model includes internal losses occurring in power stage transistors, power stage drivers and bondwires. Modeled external losses include printed circuit board resistance and inductance, inductor direct and alternating current characteristics as well as capacitor nonidealities.

Internal loss modeling was mostly based on Cadence simulations. Power stage transistors especially were thoroughly modeled. The capacitances of the power stage transistors were extracted by integrating gate and drain currents during the transistor on and off transitions. Charging of the parasitic capacitances followed the theory in turn-off and turn-on transitions and therefore the capacitance extraction was fairly simple. Nonlinearities of the parasitic capacitors were modeled in SIMPLIS with multiple linear approximations. Transistor gate drivers were very rough approximations of the real drivers but good enough for the simulation model. Drivers were modeled to match the gate currents simulated in Cadence, which were then combined the accurate switching transistor models in order to accurately model the switching characteristics.

External loss models were based on measurements and simulations. Printed circuit board losses were based on Ansys simulations in which the printed circuit board inductances and resistances were solved from the geometry of the printed circuit board. Inductors were modeled to match the datasheet impedance and resistance graphs and the model was verified against the measurements done in the laboratory. An automated measurement testbench was done for the inductor measurements using LabVIEW and the results were parsed using Matlab. A ladder topology with resistances and inductances was used in the final inductor model to model the frequency characteristics of the inductor. The effect of direct current on inductance was also investigated but the inductance reduction did not have any significant impact on efficiency. Other external components such as capacitors also cause some external losses and they were modeled based on the capacitor datasheets.

The simulation model was compared against single- and two-phase efficiency measurements with multiple different input and output voltages which were chosen to match the most common use cases. Efficiency curves were drawn for each configuration using the implemented simulation model and over 300 different comparison points were compared in total. A post processing script that was launched after a simulation completes had to be written with the programming language SIMPLIS supports to draw the efficiency graph from the simulated data. Using the script allowed to run the efficiency simulation without any additional licenses other than the SIMPLIS license. The final model achieved an average error of under 1 % between all the measured and simulated efficiency curves. The most accurate results were obtained with lower switching frequency and larger inductance.

Apart from accuracy, the simulator had to be practical and therefore the simulation time had to be considered. Simulation time was attempted to be kept at minimum by simplifying the schematic in as many ways as possible without losing accuracy. For example, reducing the point of the linear approximations in the power stage transistors from 79 points to 17 points saved nearly 50 seconds in single-phase simulations without significant changes in simulation accuracy.