Design of an Architectural Model for the Coffee Processor Using ArchC
Gual González, Daniel (2010)
2010
Tieto- ja sähkötekniikan tiedekunta
This publication is copyrighted. You may download, display and print it for Your own personal use. Commercial use is prohibited.
Hyväksymispäivämäärä
2010-09-08
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201010271345
https://urn.fi/URN:NBN:fi:tty-201010271345
Tiivistelmä
The present work is aimed to provide the clearest description possible of the COFFEE RISC core model written through the ArchC software and simulate its behaviour. In this sense, we explore the software applications used for instruction set simulation focusing on the ArchC tools and their features. According to the guidelines of this software, a cycle-accurate description of the COFFEE core architecture is developed, which is used to synthesize a timed instruction set simulator and an assembler.
Our work also contains some elements of analysis concerning the ArchC tools and the resulting instruction set simulator in order to evaluate their characteristics and capabilities for hardware architecture modeling purposes. We did not emphasize only on the features of the ArchC tools at the current status of development but also the projection of this software for future implementations. /Kir10
Our work also contains some elements of analysis concerning the ArchC tools and the resulting instruction set simulator in order to evaluate their characteristics and capabilities for hardware architecture modeling purposes. We did not emphasize only on the features of the ArchC tools at the current status of development but also the projection of this software for future implementations. /Kir10