FPGA based Ethernet media level tester
Ihamäki, Tero (2018)
Lataukset:
2018
Tietotekniikka
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2018-06-06
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201804241544
https://urn.fi/URN:NBN:fi:tty-201804241544
Tiivistelmä
Ethernet is a mature technology with wide usage area in devices communicating with each other. Internet of Things is constantly increasing the number of devices in the world-wide network. Security of aspects of these devices should be considered carefully, creating the need to test devices on Ethernet level.
This thesis presents design and implementation of a test device functioning on media level of Ethernet. By modifying, injecting and monitoring Ethernet frames transmitted on the communication media, the functionality of a device under testing can be debugged and tested in different situations. The test device is a multi-purpose communication tester, providing several possible usage areas, but is originally developed for debugging and testing purposes for a custom communication protocol used in Ethernet based automation system. At the time of writing this, the tester is already in use as a part of other test equipment of the automation system.
The tester is implemented using existing automation device, consisting four Ethernet ports and an FPGA chip. All functionality is implemented on FPGA, making the implementation work on the hardware level. This brings new possibilities compared to testing Ethernet devices with multifunctional processor based design. The tester is to be connected to the communication media between the tested devices. In a normal situation, the tester device is routing unmodified frames through it with only insignificant delays, making it invisible to surrounding devices. However, based on user commands, frames can be modified runtime or inject new frames to inputs of a device under testing.
There are some related commercial Ethernet testing devices already on the market. However, those are found to be expensive and does not provide similar features for frame modifying than the device introduced here. Main drivers for the project was to develop low cost or free testing and monitoring device with the possibility to update the features based on needs found in future.
The thesis presents basics of Ethernet with two lowest OSI-layers, functional principles of FPGA chips and other needed aspects on theory level. The theory is then followed by introducing functionalities, design, and implementation of the device. Afterwards, we take a look at the actual tests, how those function and observations noticed during testing. Lastly, we summarize briefly the thesis and consider the possible future development of the project.
This thesis presents design and implementation of a test device functioning on media level of Ethernet. By modifying, injecting and monitoring Ethernet frames transmitted on the communication media, the functionality of a device under testing can be debugged and tested in different situations. The test device is a multi-purpose communication tester, providing several possible usage areas, but is originally developed for debugging and testing purposes for a custom communication protocol used in Ethernet based automation system. At the time of writing this, the tester is already in use as a part of other test equipment of the automation system.
The tester is implemented using existing automation device, consisting four Ethernet ports and an FPGA chip. All functionality is implemented on FPGA, making the implementation work on the hardware level. This brings new possibilities compared to testing Ethernet devices with multifunctional processor based design. The tester is to be connected to the communication media between the tested devices. In a normal situation, the tester device is routing unmodified frames through it with only insignificant delays, making it invisible to surrounding devices. However, based on user commands, frames can be modified runtime or inject new frames to inputs of a device under testing.
There are some related commercial Ethernet testing devices already on the market. However, those are found to be expensive and does not provide similar features for frame modifying than the device introduced here. Main drivers for the project was to develop low cost or free testing and monitoring device with the possibility to update the features based on needs found in future.
The thesis presents basics of Ethernet with two lowest OSI-layers, functional principles of FPGA chips and other needed aspects on theory level. The theory is then followed by introducing functionalities, design, and implementation of the device. Afterwards, we take a look at the actual tests, how those function and observations noticed during testing. Lastly, we summarize briefly the thesis and consider the possible future development of the project.