HIGHHigh Speed Monolithic Level Shifter for LC Type DCDC Converter in 45nm CMOS Technology
Amin, Mehran Murtaiz (2016)
2016
Master's Degree Programme in Electrical Engineering
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
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Hyväksymispäivämäärä
2016-04-06
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201603223735
https://urn.fi/URN:NBN:fi:tty-201603223735
Tiivistelmä
Level shifter is an important building block in the power management system. In the DC-DC buck converter, requires a control signal with very low rise and fall time. Level shifters are used to convert low voltage signal to high voltage signal for the high side PMOS transistor of the power stage and allows increasing the efficiency of the DCDC buck converter with low rise and fall time.
This thesis presents High voltage tolerant level shifter using differentially switched cascode transistor topology in cascade structure. This high voltage tolerant level shifter is providing high voltage control signal to the power stage of the step down dc-dc converter. Output signal of the level shifter has an offset of 5VDD of the nominal supply voltage at high frequency with a very low power loss of 1.84mW where each VDD is 1V. P-Driver and N-Driver provides dead time controlled signal for the power stage PMOS and NMOS transistor. The dead time for the high to low side is 157ps and low to high side is 115ps. The layout of single stage level shifter is presented which consumes a silicon area of 83.54×121.86 [μm×μm] and layout of the all three stages consumes 262.82×124.66 [μm×μm] of silicon area. The converter is designed in standard 1V, Cadence 45nm Generic Process Design Kit (GPDK). The switching frequency is 52MHz. The converter operates with 6V input voltage and provides 1.25V constant output voltage. When the input power is 200mW, the extracted simulation gives a peak conversion efficiency of 79.65% with 200mA output current. All the result and the efficiency calculation are presented with PCB and package parasitic for real component.
This thesis presents High voltage tolerant level shifter using differentially switched cascode transistor topology in cascade structure. This high voltage tolerant level shifter is providing high voltage control signal to the power stage of the step down dc-dc converter. Output signal of the level shifter has an offset of 5VDD of the nominal supply voltage at high frequency with a very low power loss of 1.84mW where each VDD is 1V. P-Driver and N-Driver provides dead time controlled signal for the power stage PMOS and NMOS transistor. The dead time for the high to low side is 157ps and low to high side is 115ps. The layout of single stage level shifter is presented which consumes a silicon area of 83.54×121.86 [μm×μm] and layout of the all three stages consumes 262.82×124.66 [μm×μm] of silicon area. The converter is designed in standard 1V, Cadence 45nm Generic Process Design Kit (GPDK). The switching frequency is 52MHz. The converter operates with 6V input voltage and provides 1.25V constant output voltage. When the input power is 200mW, the extracted simulation gives a peak conversion efficiency of 79.65% with 200mA output current. All the result and the efficiency calculation are presented with PCB and package parasitic for real component.