Low Power Switched Capacitor DC-DC Converters for Low Power Transceiver Applications
Haq, Faizan Ul (2012)
2012
Master's Degree Programme in Radio Frequency Electronics
Tieto- ja sähkötekniikan tiedekunta - Faculty of Computing and Electrical Engineering
This publication is copyrighted. You may download, display and print it for Your own personal use. Commercial use is prohibited.
Hyväksymispäivämäärä
2012-02-08
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tty-201203141061
https://urn.fi/URN:NBN:fi:tty-201203141061
Tiivistelmä
DC-DC converters, also known as switching voltage regulators, are one of the main components of a power management unit. Their main role is to provide a constant, smooth output voltage to power the electronic devices. Recent miniaturi-zation trend of electronics circuitry has led to the need for smaller and high-efficient DC-DC converters in current and future applications.
This thesis presents a Switched Capacitor (SC) based DC-DC converter, which can directly operate at input voltage of 4.2V on 45nm CMOS process. Currently, most of the DC-DC converters on 45nm are not able to operate at such high volt-ages. Moreover, SC architecture has resulted in smaller size of converter com-pared with LC type DC-DC converters.
The design uses three SC topologies, which include two novel SC topologies of 2/5 and 2/7. Devices break down conditions have been overcome by implement-ing some of the MOS switches in cascoded structures. The converter structure uses eight phase interleaving approach to reduce output ripple to as low as 25mV level.
In addition to the main SC structure, a four-stage differential ring oscillator is de-signed for providing quadrature clock signals to the SC topologies. Clock genera-tor can be enabled/disabled from outside the chip, through an enable (EN) pin. For instance, the EN pin can be used for regulating the output voltage in Pulse Fre-quency Modulation (PFM) feedback approach. /Kir12
This thesis presents a Switched Capacitor (SC) based DC-DC converter, which can directly operate at input voltage of 4.2V on 45nm CMOS process. Currently, most of the DC-DC converters on 45nm are not able to operate at such high volt-ages. Moreover, SC architecture has resulted in smaller size of converter com-pared with LC type DC-DC converters.
The design uses three SC topologies, which include two novel SC topologies of 2/5 and 2/7. Devices break down conditions have been overcome by implement-ing some of the MOS switches in cascoded structures. The converter structure uses eight phase interleaving approach to reduce output ripple to as low as 25mV level.
In addition to the main SC structure, a four-stage differential ring oscillator is de-signed for providing quadrature clock signals to the SC topologies. Clock genera-tor can be enabled/disabled from outside the chip, through an enable (EN) pin. For instance, the EN pin can be used for regulating the output voltage in Pulse Fre-quency Modulation (PFM) feedback approach. /Kir12