Emulating SPI Flash With Random-Access Memory : Design and implementation of an application optimized memory controller
Martikainen, Olli (2025)
2025
Tietotekniikan DI-ohjelma - Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
Hyväksymispäivämäärä
2025-06-13
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202506127133
https://urn.fi/URN:NBN:fi:tuni-202506127133
Tiivistelmä
This work investigates the feasibility of replacing Serial Peripheral Interface (SPI) connected flash modules with a Dynamic Random Access Memory (DRAM) based emulation system and presents an implementation of a custom memory controller optimized for low latency. The primary goal is to speed up the flashing of a firmware test setup to reduce wait times for developers pushing firmware changes into a Continuous Integration software pipeline. The feasibility is in vestigated by studying the timing of the commands for the flash memory modules, focusing especially on the read operations as the writes are not as timing sensitive.
The specific flash modules studied support many different SPI bus configurations with varying speeds and widths. The two most challenging configurations that were investigated were SPI at 33 MHz frequency and Quad SPI at 66 MHz frequency. The challenge with the slower 33 MHz configuration is that there is exactly one clock cycle between the last address bit arriving and the first data being sent out. This is equal to 30 nano seconds. The deadline seems nearly impossible to meet without an application specific circuit; however, the superior bandwidth of DRAM may be utilized to be able to ease the strict timing requirement. The way to achieve this is by not waiting for the full address to arrive, which extends the available time to several times the initial, depend ing on how many bits of the address are skipped. This of course requires buffering the entirety of the address space covered by the skipped addresses, but as long as the number of skipped bits is not too high, the higher throughput of DRAM can overcome this easily.
On the 66 MHz QSPI bus the address bits arrive four at a time, and at twice the frequency, so the time afforded by skipping address bits is not enough to overcome the additional reads required by the buffering. Luckily, the flash modules also require some additional time between the address and data at this faster bus speed. The specification states four “dummy cycles”, where the clock is running but no data is transferred, between the address and data transfers. In total then there is five cycles, or 75 nano seconds between the address and data, which is tight, but manageable with dedicated hardware in the form of a Field Programmable Gate Array.
The strict timing requires all parts of the data path to be optimized for latency, which is why a custom memory controller was developed. The final memory controller achieved a latency of one cycle, in addition to the fixed delays of the DRAM. After estimating the delays in the rest of the planned emulator system, all logical blocks of the system together contributed to exactly 75 ns of latency, so the project was deemed feasible. This leaves no room for error in the estimations, however, some room for improvement was identified in the traditional fast to slow clock domain crossing, which when optimized, could allow for some additional margin if needed.
The specific flash modules studied support many different SPI bus configurations with varying speeds and widths. The two most challenging configurations that were investigated were SPI at 33 MHz frequency and Quad SPI at 66 MHz frequency. The challenge with the slower 33 MHz configuration is that there is exactly one clock cycle between the last address bit arriving and the first data being sent out. This is equal to 30 nano seconds. The deadline seems nearly impossible to meet without an application specific circuit; however, the superior bandwidth of DRAM may be utilized to be able to ease the strict timing requirement. The way to achieve this is by not waiting for the full address to arrive, which extends the available time to several times the initial, depend ing on how many bits of the address are skipped. This of course requires buffering the entirety of the address space covered by the skipped addresses, but as long as the number of skipped bits is not too high, the higher throughput of DRAM can overcome this easily.
On the 66 MHz QSPI bus the address bits arrive four at a time, and at twice the frequency, so the time afforded by skipping address bits is not enough to overcome the additional reads required by the buffering. Luckily, the flash modules also require some additional time between the address and data at this faster bus speed. The specification states four “dummy cycles”, where the clock is running but no data is transferred, between the address and data transfers. In total then there is five cycles, or 75 nano seconds between the address and data, which is tight, but manageable with dedicated hardware in the form of a Field Programmable Gate Array.
The strict timing requires all parts of the data path to be optimized for latency, which is why a custom memory controller was developed. The final memory controller achieved a latency of one cycle, in addition to the fixed delays of the DRAM. After estimating the delays in the rest of the planned emulator system, all logical blocks of the system together contributed to exactly 75 ns of latency, so the project was deemed feasible. This leaves no room for error in the estimations, however, some room for improvement was identified in the traditional fast to slow clock domain crossing, which when optimized, could allow for some additional margin if needed.