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ReImA: A Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs : Design, Verification, FPGA-based prototyping and ASIC

Soliman, Mohamed (2025)

 
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Soliman, Mohamed
2025

Tietotekniikan DI-ohjelma - Master's Programme in Information Technology
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
Hyväksymispäivämäärä
2025-03-03
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202503012508
Tiivistelmä
The advancement in electronics and semiconductors introduced the area of embedded vision systems. Embedded vision systems are systems that integrate both image-capturing and processing capabilities on the same device. These systems are widely used in robotics, security systems, autonomous vehicles, medical imaging, and industrial automation. One of the prominent kinds of camera module interfaces is MIPI CSI-2, which stands for Mobile Industry Processor Interface Camera Serial Interface Type-2. MIPI CSI-2 is a high-speed interface developed by the MIPI alliance, and it is used for transmitting image and video data from camera modules to embedded processors. MIPI CSI-2 is generally extensively used as an interface for mobile phones and handheld embedded devices. Moreover, despite the widespread development of open-source MPSoCs, there have been relatively few contributions from the open-source community toward developing a CSI-2-based camera interface that adequately addresses the needs of MPSoCs. Thus, this work proposes, to the best of our knowledge, the first open-source implementation of a reconfigurable image acquisition and processing platform for MPSoC integration. The proposed design is implemented and verified on both FPGA (Zynq ZCU104 FPGA) and ASIC (TSMC 22nm) implementation platforms and is compared against state-of-the-art hardware implementations. The hardware implementation results depict that the proposed design can support a throughput of 9.6 Gbps for streaming 4K resolution images. Furthermore, Design Space Exploration (DSE) was performed for the baseline design, and techniques for reducing the latency as well as area and power consumption are proposed. The ASIC implementation results demonstrate that the improved design results in a latency reduction of one image line, a reduction in power by 14.9%, and a reduction in area by 47.5%.
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