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Investigation of well-defined pinholes in TiO<sub>2</sub> electron selective layers used in planar heterojunction perovskite solar cells

Masood, Muhammad Talha; Qudsia, Syeda; Hadadian, Mahboubeh; Weinberger, Christian; Nyman, Mathias; Ahläng, Christian; Dahlström, Staffan; Liu, Maning; Vivo, Paola; Österbacka, Ronald; Smått, Jan Henrik (2020)

 
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Masood, Muhammad Talha
Qudsia, Syeda
Hadadian, Mahboubeh
Weinberger, Christian
Nyman, Mathias
Ahläng, Christian
Dahlström, Staffan
Liu, Maning
Vivo, Paola
Österbacka, Ronald
Smått, Jan Henrik
2020

Nanomaterials
181
doi:10.3390/nano10010181
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202003272909

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Peer reviewed
Tiivistelmä
<p>The recently introduced perovskite solar cell (PSC) technology is a promising candidate for providing low-cost energy for future demands. However, one major concern with the technology can be traced back to morphological defects in the electron selective layer (ESL), which deteriorates the solar cell performance. Pinholes in the ESL may lead to an increased surface recombination rate for holes, if the perovskite absorber layer is in contact with the fluorine-doped tin oxide (FTO) substrate via the pinholes. In this work, we used sol-gel-derived mesoporous TiO<sub>2</sub> thin films prepared by block co-polymer templating in combination with dip coating as a model system for investigating the effect of ESL pinholes on the photovoltaic performance of planar heterojunction PSCs. We studied TiO<sub>2</sub> films with different porosities and film thicknesses, and observed that the induced pinholes only had a minor impact on the device performance. This suggests that having narrow pinholes with a diameter of about 10 nm in the ESL is in fact not detrimental for the device performance and can even, to some extent improve their performance. A probable reason for this is that the narrow pores in the ordered structure do not allow the perovskite crystals to form interconnected pathways to the underlying FTO substrate. However, for ultrathin (~20 nm) porous layers, an incomplete ESL surface coverage of the FTO layer will further deteriorate the device performance.</p>
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Kalevantie 5
PL 617
33014 Tampereen yliopisto
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Kalevantie 5
PL 617
33014 Tampereen yliopisto
oa[@]tuni.fi | Tietosuoja | Saavutettavuusseloste