Investigation of posits and IEEE-754 floating points : In hardware implementations of addition and multiplication operations
Kylväjä, Juho (2023)
2023
Sähkötekniikan DI-ohjelma - Master's Programme in Electrical Engineering
Informaatioteknologian ja viestinnän tiedekunta - Faculty of Information Technology and Communication Sciences
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Hyväksymispäivämäärä
2023-05-16
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202304244205
https://urn.fi/URN:NBN:fi:tuni-202304244205
Tiivistelmä
This thesis aims to investigate a relatively new alternative presentation for floating-point arithmetic the type-3 UNUM, posit for a replacement of the widely used IEEE 754 floating-point standard. The thesis's main focus is on arithmetic operations of addition and multiplication. First, literature check of posit and IEEE 754 floating-point standards formats, special cases, overflow and underflow operations, and rounding methods are conducted. Then the arithmetic implementation steps of posit and IEEE 754 addition and multiplication operations on hardware are shown. In addition, the tools used to analyze the chosen designs and the designed testbench flow for behavioral verification of the designs is described. Finally, the results were examined, followed by the conclusion.
The thesis concludes that posits could replace the currently widely used IEEE 754 standard due to having better accuracy around one and better dynamic range with 8, 16 and 32-bit numbers. However, the synthesis results show that FPU achieves better area, delay and power scores than the posit designs chosen in this thesis. Furthermore, implementing compatible processors for posits would require lots of work and time. Overall, posits have great potential to replace the IEEE 754 standard. It is interesting to see how future studies on posits will affect the future of floating-point arithmetic in hardware.
The thesis concludes that posits could replace the currently widely used IEEE 754 standard due to having better accuracy around one and better dynamic range with 8, 16 and 32-bit numbers. However, the synthesis results show that FPU achieves better area, delay and power scores than the posit designs chosen in this thesis. Furthermore, implementing compatible processors for posits would require lots of work and time. Overall, posits have great potential to replace the IEEE 754 standard. It is interesting to see how future studies on posits will affect the future of floating-point arithmetic in hardware.