Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters
Ghosh, Agnimesh; Spelman, Andrei; Cheung, Tze Hin; Boopathy, Dhanashree; Unnikrishnan, Vishnu; Lampu, Vesa; Xu, Guixian; Anttila, Lauri; Stadius, Kari; Kosunen, Marko; Ryynänen, Jussi (2022)
Ghosh, Agnimesh
Spelman, Andrei
Cheung, Tze Hin
Boopathy, Dhanashree
Unnikrishnan, Vishnu
Lampu, Vesa
Xu, Guixian
Anttila, Lauri
Stadius, Kari
Kosunen, Marko
Ryynänen, Jussi
Teoksen toimittaja(t)
Nurmi, Jari
Wisland, Dag T.
Aunet, Snorre
Kjelgaard, Kristian
IEEE
2022
2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202302082180
https://urn.fi/URN:NBN:fi:tuni-202302082180
Kuvaus
Peer reviewed
Tiivistelmä
To impose the reconfigurability and reusability of digital circuits for millimeterwave transmitter architectures, high-speed digital signal processing architectures are explored. The digital front-end of these next-generation transmitters can be implemented up to the maximum operating frequency to meet the requirements of the 5G NR FR2 frequency bands. This paper presents an efficient implementation of a reconfigurable digital signal processor (DSP) that contains programmable multistage multirate filters, operable up to 4 GHz, and a flexible generator for polar, outphasing, and multilevel outphasing modulation. The system achieves an excellent ACLR of 42 dB and EVM degradation of 1.61% with a 7-bit phase signal at a sampling frequency of 4 GHz for outphasing modulation. Digital synthesis of the circuit in a 22 nm FDSOI process results in a core area of 0.12 mm2and an estimated power consumption of 142 mW for a 200 MHz bandwidth 5G NR baseband signal.
Kokoelmat
- TUNICRIS-julkaisut [16977]