Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures
Vadivel, Kanishkan; de Bruin, Barry; Jordans, Roel; Corporaal, Henk; Jääskeläinen, P. (2022)
Vadivel, Kanishkan
de Bruin, Barry
Jordans, Roel
Corporaal, Henk
Jääskeläinen, P.
IEEE
2022
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202301251706
https://urn.fi/URN:NBN:fi:tuni-202301251706
Kuvaus
Peer reviewed
Tiivistelmä
Exposed Datapath Architectures (EDPAs) with aggressively pruned data-path connectivity, where not all function units in the design have connections to a centralized register file, are promising solutions for energy-efficient computation. A direct bypassing of data between function units without temporary copies to the register file is a prime optimization for programming such architectures. However, traditional compiler frameworks, such as LLVM, assume function-units connect to register-files and allocate all live variables in register-files. This leads to schedule inefficiencies in terms of instruction-level parallelism and reg-ister accesses in the EDPAs. To address these inefficiencies, we propose Prebypass; a new optimization pass for EDPA compiler backends. Experimental results on an EDPA class of architecture, Transport- Triggered Architecture, show that Prebypass improves the runtime, register reads, and register writes up to 16%, 26 %, and 37 % respectively, when the datapath is extremely pruned. Evaluation in a 28-nm FDSOI technology reveals that Prebypass improves the core-level Energy by 17.5 % over the current heuristic scheduler.
Kokoelmat
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