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Unified OpenCL Integration Methodology for FPGA Designs

Leppänen, Topi; Mousouliotis, Panagiotis; Keramidas, Georgios; Multanen, Joonas; Jääskeläinen, Pekka (2021)

 
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Leppänen, Topi
Mousouliotis, Panagiotis
Keramidas, Georgios
Multanen, Joonas
Jääskeläinen, Pekka
IEEE
2021


2021 IEEE Nordic Circuits and Systems Conference (NorCAS)
This publication is copyrighted. You may download, display and print it for Your own personal use. Commercial use is prohibited
doi:10.1109/NorCAS53631.2021.9599861
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202111298778

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Peer reviewed
Tiivistelmä
OpenCL is a widely adopted open standard for general purpose programming of diverse heterogeneous parallel platforms that can harness various device types such as CPUs, DSPs, GPUs, FPGAs and hardware accelerators. It is an extensive and explicit low level API serving well as a platform portability layer. However, using OpenCL for diverse heterogeneous programming in multi-vendor platforms is not practical due to device vendors each providing their own OpenCL implementations which do not interoperate efficiently, leading to inefficient execution coordination and collaborative execution between various device types from different vendors. To this end, this paper proposes a vendor-independent open source method for integration of custom FPGA components to a common OpenCL platform. The method relies on a streamlined memory-mapped hardware control interface implemented by the integrated components. The required OpenCL driver integration is then automatically provided, enabling easy inclusion of different types of FPGA accelerators to the control of a single OpenCL runtime. The ease of integration and portability is demonstrated by integrating two hardware devices in two different FPGA devices. The resource overhead of the hardware interface is shown to be negligible and the clock frequency overheads small enough to not pose efficiency challenges.
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