Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems
Ahovainio, Sami; Mercat, Alexandre; Viitanen, Marko; Vanne, Jarno (2020)
Ahovainio, Sami
Mercat, Alexandre
Viitanen, Marko
Vanne, Jarno
IEEE
2020
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-202102041926
https://urn.fi/URN:NBN:fi:tuni-202102041926
Kuvaus
Peer reviewed
Tiivistelmä
High Efficiency Video Coding (HEVC) creates the conditions for cost-effective video transmission and storage but its inherent computational complexity calls for efficient parallelization techniques. This paper provides HEVC encoders with a holistic parallelization scheme that exploits parallelism at data, thread, and process levels at the same time. The proposed scheme is implemented in the practical Kvazaar open-source HEVC encoder. It makes Kvazaar exploit parallelism at three levels: 1) Single Instruction Multiple Data (SIMD) optimized coding tools at the data level; 2) Wavefront Parallel Processing (WPP) and Overlapped Wavefront (OWF) parallelization strategies at the thread level; and 3) distributed slice encoding on multi-computer systems at the process level. Our results show that the proposed process-level parallelization scheme increases the coding speed of Kvazaar by 1.86× on two computers and up to 3.92× on five computers with +0.19% and +0.81% coding losses, respectively. Exploiting all these three parallelism levels on a five-computer setup gives almost a 25× speedup over a non-parallelized single-core implementation.
Kokoelmat
- TUNICRIS-julkaisut [19767]