Kvazaar 4K HEVC Intra Encoder on FPGA Accelerated Airframe Server
Sjövall, Panu; Viitamäki, Vili; Oinonen, Arto; Vanne, Jarno; Hämäläinen, Timo D.; Kulmala, Ari (2017)
Sjövall, Panu
Viitamäki, Vili
Oinonen, Arto
Vanne, Jarno
Hämäläinen, Timo D.
Kulmala, Ari
IEEE
2017
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:tuni-201911186023
https://urn.fi/URN:NBN:fi:tuni-201911186023
Kuvaus
Peer reviewed
Tiivistelmä
This paper presents a real-time Kvazaar HEVC intra encoder for 4K Ultra HD video streaming. The encoder is implemented on Nokia AirFrame Cloud Server featuring a 2.4 GHz dual 14-core Intel Xeon processor and Arria 10 PCI Express FPGA accelerator card. In our HW/SW partitioning scheme, the data-intensive Kvazaar coding tools including intra prediction, DCT, inverse DCT, quantization, and inverse quantization are offloaded to Arria 10 whereas CABAC coding and other control-intensive coding tools are executed on Xeon processors. Arria 10 has enough capacity for up to two instances of our intra coding accelerator. The results show that the proposed system is able to encode 4K video at 30 fps with a single intra coding accelerator and at 40 fps with two accelerators. The respective speed-up factors are 1.6 and 2.1 over the pure Xeon implementation. To the best of our knowledge, this is the first work dealing with HEVC intra encoder partitioned between CPU and FPGA. It achieves the same coding speed as HEVC intra encoders on ASIC and it is at least 4 times faster than existing HEVC intra encoders on FPGA.
Kokoelmat
- TUNICRIS-julkaisut [16977]