"quasi-delay-insensitive" - Selaus asiasanan mukaan Kandidaatintutkielmat
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Synthesis of Digital Quasi-Delay-Insensitive Greatest Common Divisor Circuit
(2024)
KandidaatintyöThis work investigates the design of digital asynchronous quasi-delay-insensitive circuits with a focus on the methodology developed by Alain Martin [22]. While synchronous circuits have a global clock signal that drives ...
